Physical Design Engineer

Job Summary

We are looking for experienced Physical Design Engineers to join our client semiconductor engineering team. The successful candidates will be responsible for block-level and/or full-chip physical implementation from netlist through GDSII/tape-out, with strong ownership of timing closure, physical verification and signoff activities.

Our client works on advanced semiconductor designs, including high-performance and low-power SoCs and complex IP/subsystems. Its published capabilities include advanced-node designs down to 3nm and timing closure for designs up to 3GHz.

Key Responsibilities

• Own and execute block-level and/or full-chip Physical Design from netlist to GDSII.

• Perform:

  • Floorplanning

  • Power planning

  • Placement and optimization

  • Clock Tree Synthesis (CTS)

  • Routing

  • Post-route optimization

• Drive timing closure across multiple modes and corners (MCMM), including setup and hold.

• Analyze and resolve:

  • Timing violations

  • Congestion

  • Signal Integrity (SI)

  • Power-related issues

  • Physical design violations

• Perform DRC/LVS and physical verification activities and ensure signoff quality.

• Perform IR Drop and Electromigration (EM) analysis.

• Work closely with STA, RTL, DFT, Verification and other cross-functional teams.

• Collaborate with STA teams on setup/hold closure and ECO implementation.

• Support tape-out and customer deliverables.

• Participate in design reviews and contribute to improvement of physical design flows and methodologies.

• For senior-level candidates, provide technical guidance and mentoring to junior engineers.

Job Requirements

• Bachelor's/Master's Degree in Electrical & Electronic Engineering, Electronics Engineering, Computer Engineering, or related discipline.

• 5+ years of hands-on experience in Physical Design / VLSI Backend for Senior Engineer level.

• 8+ years of experience for experienced Senior/Lead-level candidates.

• Strong hands-on experience in RTL/netlist-to-GDSII physical implementation.

• Strong understanding of:

  • Floorplanning

  • Placement

  • CTS

  • Routing

  • Timing closure

  • Physical verification

  • Power integrity

• Experience working with advanced/low technology nodes is highly preferred.

• Experience with MCMM timing closure and ECO implementation.

• Experience with DRC/LVS, IR Drop and EM signoff.

• Good understanding of low-power design and PPA (Power, Performance and Area) optimization.

• Strong analytical and problem-solving skills.

Preferred Technical Skills

Experience with industry-standard EDA tools such as:

• Synopsys ICC2 / Fusion Compiler / PrimeTime

• Cadence Innovus / Tempus

• Mentor/Siemens Calibre

• Ansys power integrity tools

• TCL / Perl / Python scripting

Add Advantage

• Intel flow / Intel PDK experience

• Advanced-node experience such as 7nm, 5nm, 3nm

• Full-chip ownership

• Multiple successful tape-out experience

• High-frequency/high-performance designs

• Low-power implementation

• Experience with complex SoCs, processors, graphics, PCIe, CXL, DDR or automotive designs

• Experience working with international semiconductor customers